A New Low Power and High Speed Bidirectional Shift Register Architecture

In this paper a new, low power and high speed Bidirectional Shift Register (BSR) architecture is presented. It can be used for the design and the implementation of hard arithmetic operations. Reconfigurable computing, and cryptographic algorithms are two application examples where by using the new BSR their power and speed can be improved. Comparing to the conventional design, the proposed achieves 19-42 % power consumption reduction with simultaneous 25% reduction of the covered area. So the new design fits perfectly in designs with hard specifications of power dissipation and covered area (e.g. wireless). The whole design was captured by using VHDL language, and for the synthesis a 0.7 um CMOS standard cell library was used. The power measurements were taken with a custom design tool that was developed in our laboratory.